This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 11-282404, filed Oct. 4, 1999; and No. 11-282405, filed Oct. 4, 1999, the entire contents of which are incorporated herein by reference.
The present invention relates to a damascene structure and a CMP process for forming the damascene structure and, more particularly, to a structure of a barrier film on the upper surface of a Cu wiring and a CMP process for forming the barrier film structure. The invention is directed to achieve reduction in capacity between wirings, assurance of oxidation resistance and preventability of diffusion of Cu, and suppression of increase in wiring resistance.
A semiconductor device in recent years employs a damascene wiring (including a plug) structure from the viewpoints of size reduction and so on. In a multi-level damascene wiring structure, in order to prevent oxidation and diffusion of a metal filled in a groove, to provide an etching stopper and to reduce contact resistance, and so on, it is necessary to provide a cap film made of a material different from the material of the wiring on the upper surface of the wiring. It is important that the cap film is thin. One of the reasons is to prevent deterioration of the wiring performance (or plug performance), specifically, to minimize an RC delay. Another reason is that it is difficult from a process viewpoint to form a wiring (or plug) having a high aspect ratio, that is, a thick film.
The damascene structure will be described hereinbelow by using a wiring as an example. In a conventional technique, a groove for wiring is formed in an insulating film and is filled with a wiring material, thereby forming a wiring. After that, the wiring is etched only by a thickness corresponding to the thickness of a cap film to be formed, thereby forming a recess on the upper surface of the wiring. After that, the material of the cap film is deposited on the entire surface of the semiconductor substrate. By removing the cap film on a field region by CMP (chemical mechanical polishing), the cap film is left only in the groove for wiring. In such a manner, the cap film is formed by being embedded in the groove for wiring.
According to the conventional method, however, dishing is caused by the CMP in the cap film on the wiring and controllability with respect to the thickness of the cap film is low. For example, when the width of a wiring is set to 5 xcexcm, although a cap film having a thickness of 40 nm is tried to be formed, as shown in FIG. 1, the thickness of the cap film becomes 15 nm in practice which is less than the half of the desired value. In an area where the wiring width is wider than 5 xcexcm, the cap film formed is much thinner. That is, the wiring width dependency on the thickness of the cap film is large, the process controllability is low, and a desired film thickness cannot be obtained in an area where the wiring width is large.
In a further conventional technology, therefore, in the case of making the thickness of the cap film constant, a large amount of the recess is formed in the wiring, so that it is possible that a cap film having a desired thickness can be formed. According to the conventional method, however, the surface of a semiconductor substrate after the cap film on the field region is removed by CMP is very rough, and also the cap film remains on side wall of the groove. It causes the following problems. For example, a deviation occurs between the damascene wiring and a via hole formed on the damascene wiring, so that the contact material with which the via hole is filled is not sufficiently filled and the contact resistance increases. In the case where the cap film is conductive, the electrode area as a capacitor increases only by an amount corresponding to the residual cap film on the side walls of the groove. Consequently, the capacity between wirings increases and the RC delay of the wiring increases.
As described above, the conventional damascene structure and the CMP process for forming the conventional damascene structure have the problem caused by the dishing of the cap film as described in the first conventional example and the problem caused by the residual cap film on the side walls of a groove as described in the second conventional example. The problems obstruct improvement in characteristics. It is an object of the invention to if provide a semiconductor device having an excellent RC characteristic by forming a cap film while avoiding the problems.
Hitherto, a TiN film, a TaN film, for example, are proposed to be employed as a film of preventing diffusion of Cu deposited on the surface of a Cu wiring. In order to realize the structure, the upper portion of the Cu wiring formed in the groove of the insulating layer is removed so that the Cu wiring is recessed from a level of the upper surface of the insulating film. Subsequently, a barrier film is formed on the entire surface of a semiconductor substrate. After that, the barrier film on the field region of the insulating film is removed by chemical mechanical polishing (CMP). The barrier film on the Cu film is, however, easily influenced by the state of the surface of the Cu film. It follows that that the diffusion preventability deteriorates in a rough portion caused by particles in the surface of the Cu film and a step portion between the insulating film and the wiring. In some cases, a defect occurs in the barrier layer by dishing and a damage at an edge portion at the time of CMP for forming the barrier layer. In order to ensure sufficient diffusion preventability even when a defect occurs, the barrier film has to be formed thick. Furthermore, the polishing speed of CMP varies in the surface of the wafer. The barrier film therefore has to be thick enough to ensure a high diffusion preventability and, in addition, to compensate the variation. Since such an increase in the thickness of the barrier film reduces the thickness of the wiring in the groove for wiring, effective wiring resistance (wiring resistance for the volume of the groove) increases. Although it can be considered to deepen the groove in order to decrease the wiring resistance, in this case, the aspect ratio becomes higher. It increases not only the load of processing the groove and filling Cu but also the capacity between wirings since the facing areas of the wirings are enlarged.
It is therefore another object of the invention to provide a barrier film having the structure which can avoid the problems and to suppress diffusion of Cu into an insulating interlayer without increasing the capacity between wirings.
According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a step of forming an insulating film on a semiconductor substrate; a step of forming a groove in the insulating film; a step of filling the groove with a wiring material; a step of performing CMP to form a filled wiring; a step of etching the filled wiring material to thereby form a recess; a step of depositing a cap film on the recess formed by etching the wiring material; a first polishing step of performing a polishing operation at selectivity of R1 (=removal rate for the cap film/removal rate for the insulating film); and a second polishing step of performing a polishing operation at selectivity of R2 (=removal rate for the cap film/removal rate for the insulating film), wherein each of the first polishing step and the second polishing step is performed by using a slurry having a condition of R1 greater than R2.
According to the invention, the cap film can be formed in a state where occurrence of dishing on the damascene wiring is suppressed as much as possible.
Preferably, the depth of the recess formed by etching the wiring material is larger than the thickness of the cap film. By satisfying the condition that the recess depth is larger than the thickness of the cap film, occurrence of dishing in the cap film can be suppressed as much as possible in the first polishing step.
In the method of manufacturing a semiconductor device according to the first aspect of the present invention, it is preferable that R1 in the first polishing step is equal to or larger than 1 and R2 in the second polishing step is equal to or smaller than 1.
In the method of manufacturing a semiconductor device according to the first aspect of the present invention, it is preferable that a main component of the cap film is any of Ti, Ta, Nb, W, Cr, V, Pt, and Ru, a nitride, an oxide, a boride, and an alloy of any of the elements, and a mixture of the elements.
In the method of manufacturing a semiconductor device according to the first aspect of the present invention, it is preferable that a main component of the cap film is any of Si, an Si oxide and an Si nitride, or the cap film is a fluorine-doped oxide film or poly-methyl-siloxane.
In the method of manufacturing a semiconductor device according to the first aspect of the present invention, it is preferable that a main component of the wiring material is any of Al, Cu, W, Ru, Ag, Mo, and Si, a nitride, an oxide, a boride and an alloy of any of the elements, and a mixture of any of the elements.
According to a second aspect of the present invention, there is provided a semiconductor device comprising: an insulating film formed on a semiconductor substrate; a groove formed in the insulating film; a first conductive film formed on inner walls of the groove; a second conductive film formed on the inner walls via the first conductive film; and a third conductive film formed so as to cover the upper of the second conductive film, wherein the level of the surface of the insulating film near the first conductive film is gradually lowered from a position close to the first conductive film.
According to a third aspect of the present invention, there is provided a semiconductor device comprising: a first insulating film formed on a semiconductor substrate; a groove formed in the first insulating film; a second insulating film formed on inner walls of the groove; a conductive film formed n the inner walls via the second conductive film; and a third insulating film formed so as to cover the upper of the conductive film, wherein the surface of the first insulating film and the surface of the third insulating film in the center portion of the groove are almost at the same level, and the surface of the second insulating film and ends of the third insulating film are higher than the level.
According to a fourth aspect of the present invention, there is also provided a semiconductor device having a filled Cu wiring structure formed in an insulating film, wherein a layer made of Al or an Al alloy is formed on the upper surface of a Cu wiring portion via an intermediate layer.
As described above, by using the structure in which a layer made of Al or an Al alloy is formed on the upper surface of a Cu wiring via an intermediate layer, even if Cu is leaked, Cu is captured in the Al layer. Consequently, diffusion of Cu is suppressed. Since Al has low resistance, even when an Al layer is formed thick to assure margin or the like, increase in the effective resistance caused by a barrier layer formed on the wiring can be minimized.
Preferably, the intermediate layer contains at least one element selected from Ti, Zr, V, W, Ta, Nb, Cr, Sn, Co and Ru.
Each of the elements has the function of preventing diffusion of Al into the Cu wiring, thereby preventing increase in wiring resistance.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.